As is well known, electronic memory devices using a single power supply, such as Flash Electrically Erasable Programmable Read-Only Memories (EEPROMs) having a 3 Volt main power supply, require positive voltages higher that the main power supply for the reading, writing and erasing phases and negative voltages less than the ground voltage reference for the reading and erasing phases. Voltage multipliers or charge pump circuits are widely used in these semiconductor electronic devices to internally generate voltage supplies with values higher or less than a main power supply. Many prior art approaches use charge pump circuits to provide the above required voltage values.
One such approach is disclosed in an article reported on the IEEE Journal of Solid State Circuits, Vol. SC-11, No. 3, June 1976. This approach relates to a voltage multiplier circuit using MOS technology as shown in FIG. 1. A multiplier chain is implemented using diode-connected P-channel MOS transistors. The nodes of the diode chain are coupled to the circuit inputs via capacitors in parallel. FIG. 1 shows just a portion of the diode chain including two transistors M1, M2 and two coupling capacitors C1, C2. Two non-overlapping clock pulses Phase A and Phase B are capacitively coupled to the transistors gates. The clocks are generated by two cascade MOS inverters driven by an oscillator circuit.
The multiplier operates by pumping packets of charge along the diode chain as the coupling capacitors are successively charged and discharged during each half of the clock cycle. The circuit portion shown in FIG. 1 may be considered as a single stage and a number of multiplier stages may be connected between the circuit inputs and outputs.
This first kind of charge pump circuit is also known as a two phase diode architecture parallel charge pump and presents some advantages since the maximum voltage applied to a pump capacitor is given by the absolute value of the minimum voltage which is present inside the pump circuit. The current drive capability is also independent from the number of multiplier stages. For instance, if we consider an--stage pump with a single positive main voltage supply Vdd and a ground reference, the output voltage would be:
Vout=-(N * (Vdd-Vtp)-Vtp) PA1 Vs=N * (Vdd-Vtp)=N times the single stage voltage gain. PA1 Vout-(N* Vdd-Vtp) PA1 Vs=N * Vdd=N times the single stage voltage gain PA1 Vout=-(N*(Vdd-Vtp)-Vtp) PA1 Vs=2 * (Vdd-Vtp)=2 times the single stage voltage gain.
where Vtp is the absolute value of the P-Channel MOS threshold voltage. The maximum voltage drop Vs on last coupling capacitor, the one closer to the output load, is given by:
Notwithstanding these advantages over other previous techniques, this known charge pump requires the integration of high value capacitors which occupy a large integrated circuit area.
A second approach is disclosed in U.S. Pat. No. 5,126,808 to Montalvo which relates to Flash EEPROM array architecture including a four phase parallel charge pump circuit. FIG. 2 shows a simplified schematic diagram of a negative charge pump circuit according to this second prior art approach. FIG. 2A shows a couple of stages of the FIG. 2 charge pump.
This multiplier chain is implemented using P-Channel MOS transistors. Each stage includes several transistors connected together and having their respective gate terminals connected to a corresponding coupling capacitor. FIG. 2A shows a first stage including transistors M1 and M2 coupled to corresponding capacitors C1, C2 and a subsequent stage including transistors M3, M4 coupled to corresponding capacitors C3, C4. The capacitor C1 is much smaller than the other capacitor C2 (C1&lt;&lt;C2). The same applies for the capacitor C3 which is much smaller than the other capacitor C4 (C3&lt;&lt;C4). Four clock pulses Phase A, Phase B, Phase C and Phase D are capacitively coupled to the transistor gates of the stages via the capacitors C1, C2, C3 and C4.
Every stage gains a voltage equal to the main supply voltage Vdd. If we consider a pump circuit including N stages and a capacitive load, the final multiplied voltage is:
The maximum voltage drop Vs on last coupling capacitor, the one closer to the output load, is given by:
Therefore, even with this second approach the voltage drop on the coupling capacitor is relatively high and generally requires substituting each capacitor with the series of two capacitors having doubled capacitance to improve the reliability of the circuit, but increasing the integrated circuit area.
A third prior art approach is known as Cockcroft-Walton voltage multiplier and is disclosed again in the article reported in the IEEE Journal of Solid State Circuits, Vol. SC-11, No. 3, June 1976. This approach is also known as a two phase diode architecture stacked charge pump and requires coupling discrete capacitors C which are connected serially and are much greater than stray capacitors Cs, as shown in FIG. 3.
The final multiplied voltage of N stages is:
The maximum voltage drop Vs on a coupling capacitor is given by:
Unfortunately, this type of multiplier is not adequate for integration in monolithic form since it requires high value capacitances.